The present invention relates generally to problems associated with differential thermal effects caused by power imbalances in integrated circuit chips, and particularly to circuits and techniques for reducing the time required for recovery from such differential thermal effects.
It is well known that certain transient or steady-state large-signal input conditions can cause circuit operation that creates large power imbalances within an integrated circuit. In some cases, the integrated circuit must be operated so as to allow it sufficient time to “recover” from the large power imbalances before proper circuit operation can continue. The power imbalances can cause a temporary temperature imbalance between different regions of the integrated circuit that substantially changes the operating characteristics of circuit components, such as transistors, located in the regions of the temperature imbalance. This may result in unacceptably inaccurate circuit performance until sufficient “recovery time” has elapsed to allow the temperature to be balanced between the regions.
Various other conditions are known to cause similar imbalanced thermal conditions in integrated circuit chips. For example, large-signal slewing conditions or transient imbalances may cause recovery settling “tails” in the output response of a circuit. Input signal overdrive conditions beyond the linear range of an amplifier and its feedback loop may result in thermal imbalance conditions of long duration. Also, various special-purpose applications that may cause linear feedback in an amplifier circuit to be interrupted or limited (e.g. sample/hold amplifiers, peak detector circuits, and limiting/clamping amplifiers) can cause thermal imbalance conditions of the kind referred to above in an integrated circuit. Although a thermal imbalance condition can occur due to simple transient slewing, it may be most problematic in applications in which a feedback loop is interrupted for a relatively long interval, for example in a sample/hold amplifier, a peak detector circuit, a limiting or clamping amplifier, or a multiplexed amplifier. In some cases the effects of such thermal imbalance can be reduced.
However, in the case of non-feedback integrated circuits such as voltage comparators, the duration and magnitude of thermal imbalance ordinarily would not be reduced and are dependent only on the characteristics of the differential input signal of the comparators. For example, a comparator in an ADC (analog to digital converter) usually remains or “dwells” in a highly unbalanced state most of the time and it is necessary, at a point near the end of a particular step of the ADC conversion process, that the comparator not be still undergoing a thermal recovery from the previous step of the conversion process because the error due to ongoing thermal recovery could exceed the magnitude of the comparator input signal to be discriminated. Of course, this could result in inaccurate bit decisions. U.S. Pat. No. 5,247,210 entitled “Method and Circuitry for Decreasing the Recovery Time of an MOS Differential Voltage Comparator” issued Sep. 21, 1993 to Swanson describes a technique for decreasing the recovery time on an MOS differential voltage comparator, but does not address thermal mismatch issues.
FIG. 1 shows a conventional closed loop feedback network that includes an operational amplifier 1 which receives a differential input signal Vin applied between a (−) input conductor 3 and a (+) input conductor 4. The input conductors 3 and 4 are connected to the inputs of a differential input transistor pair in circuitry 2A of an input stage 2 of amplifier 1. Input stage 2 also may include either additional components which convert a differential input current from the input transistor pair into a voltage signal provided to a subsequent stage, or alternatively may include a folded cascode circuit, the output of which drives the high impedance compensation node 5 (i.e., “comp node” 5 of folded cascode stage 2A). Comp node 5 is connected to the input of a conventional output driver circuit 6A of an output stage 6. Output driver circuit 6A produces an output signal Vout on conductor 7, which is connected to the input of a feedback network 8 (which often is simply a feedback resistor). The output of feedback network 8 is connected to inverting input 3.
FIG. 2A shows a schematic diagram of a conventional differential input circuit and folded cascode stage which can be used as input stage 2 of FIG. 1. Referring to FIG. 2A, Vin− is applied to the base of an NPN input transistor Q1, and Vin+ is applied to the base of an NPN input transistor Q2, the emitter of which is coupled by conductor 27 to the collector of an NPN current source transistor Q12. The emitter of transistor Q12 is coupled by a resistor R3 to a power supply voltage VEE. The emitter of input transistor Q1 is connected by conductor 26 to the collector of a current source transistor Q11, the emitter of which is coupled by a resistor R2 to VEE. A resistor R1 is connected between conductors 26 and 27. The bases of current source transistors Q11 and Q12 are connected to a bias voltage VB1 on conductor 22. The collector of input transistor Q1 is coupled by a conductor 24 to the emitter of a folded cascode PNP transistor Q6 and to one terminal of a resistor R5 coupled between conductor 24 and a power supply voltage VCC. Similarly, the collector of input transistor Q2 is coupled by a conductor 25 to the emitter of a folded cascode PNP transistor Q5 and to one terminal of a resistor R4 coupled between conductor 24 and VCC. The bases of cascode transistors Q5 and Q6 are connected to a bias voltage VB2 by conductor 28. Typically, the high impedance compensation or “comp” node of the entire circuit 2 is the collector of transistor Q6. In FIG. 2A, the collector of transistor Q5 is coupled to an input of a current mirror 30. The collector of transistor Q6 is connected by conductor 5 to an output of current mirror 30. The voltage on comp node conductor 5 is labeled Vcomp. If desired, a technique referred to as “re-cascoding” can be used wherein the collector of transistor Q5 is connected to the emitter of a PNP cascode transistor Q9, the collector of which is connected to current mirror 30, as shown in dashed lines. The collector of transistor Q6 is connected to the emitter of a PNP cascode transistor Q10, the collector of which is connected to another terminal of current mirror 30, as shown in dashed lines. The bases of cascode transistors Q9 and Q10, if provided, are connected to a suitable bias voltage VB3.
In the conventional closed loop feedback network of FIG. 1, the differential input error voltage is forced by the feedback loop to be nearly zero. Therefore, input stage 2 is driven to a balanced condition. Typical symmetrical construction of such circuitry on the integrated circuit chip and, along with the balanced operating condition due to the nearly-zero error voltage value of Vin, results in a thermally balanced condition of each of the power-dissipating circuit elements with respect to corresponding balanced components on the other side of the symmetrical construction.
However, if the differential input voltage Vin between the bases of transistors Q1 and Q2 is excessively large, then one of transistors Q1 and Q2 either carries no current or much less current than the other, and therefore temporarily dissipates a much different amount of power than the normal amount of power, therefore increasing the temperature difference between regions in transistors Q1 and Q2, respectively. Computer analysis and laboratory measurements have shown that the increased temperature can result in significant thermally-induced offset voltages associated with transistors Q1, Q2, Q5 and Q6. The effect of this on the recovery time of output voltage Vout (FIG. 1) appears in the waveform “A” shown in FIG. 6.
For example, if Vin+ is much larger than Vin−, then input transistor Q1 is turned off and dissipates no power. Meanwhile, a large current flows through input transistor Q2, causing it to dissipate a large amount of power. This results in substantially higher temperature in the emitter-base junction of input transistor Q2 than in input transistor Q 1, which can substantially change the operating characteristic of transistor Q2 relative to transistor Q1. After the above described Vin input overdrive condition ends, the feedback loop causes the error voltage Vin=Vin+−Vin− to be essentially zero so the feedback loop is properly balanced, and an amount of time, referred to as the “thermal recovery time” or “thermal tail”, is required for input transistors Q1 and Q2 to thermally recover to substantially the same temperature so the thermally sensitive circuitry including transistors Q1 and Q2 is balanced and the thermally-induced input offset voltage settles to a negligible value. Only then can a reliable precise value of Vout be obtained from the feedback amplifier. However, the thermal recovery time or “tail” shown in waveform “A” of FIG. 6 may be unacceptably long. Furthermore, during the Vin overdrive condition the same current flowing through transistor Q2 is subtracted from the current flowing through cascode transistor Q5, which reduces the power dissipation in transistor Q5. This causes a thermal imbalance between cascode transistors Q5 and Q6.
It should be appreciated that in a comparator there is no feedback mechanism to drive the input transistors back to a balanced condition with equal input voltages. Therefore, after a comparator decision process, the comparator remains in unbalanced condition until the next comparator decision is made. If the comparator inputs are nearly equal, there is a risk of the comparator making a wrong decision because of the input offset error caused by the thermal imbalance between the comparator input transistors.
Various techniques have been used for providing symmetrical circuit architectures and corresponding integrated circuit topography layouts to achieve thermal balance in integrated circuits, in recognition of the fact that thermal imbalance can cause lack of precision in circuit operation. That is, integrated circuit layout symmetry generally is associated with precision of circuit operation. It is a widely accepted practice that in integrated circuits for analog signal processing it is necessary to have well balanced circuit architectures and topography layouts which are generally symmetrical about various “centerlines” of the integrated circuit chip. Good analog integrated circuit design practice recognizes that this is necessary to achieve precision DC circuit operation and stability, predictable signal settling times, and reduced signal distortion. (While this is generally true in voltage feedback operational amplifiers, it is somewhat less true in current feedback operational amplifiers, due to high-impedance inputs and low-impedance output of the input stage of a current feedback operational amplifier.)
As an example, symmetry of architecture and the corresponding integrated circuit layout topography is needed for precision of DC circuit operation when a differential circuit is in an “idle” condition wherein the differential input signal is zero. The symmetry of circuit architecture and of layout topography also is needed when the circuit is “modulated” from the idle condition by an input signal in order to achieve low signal distortion, fast, clean signal settling, and low thermal “hysteresis” or “thermal history” when the modulating input signal returns to a low value. (The term “thermal hysteresis” or “thermal history” may refer to the way a transition such as a switching point voltage or “trip point” of a differential input stage is changed by the existing state of the differential input stage, for example so that the differential input signal has to increase beyond the normal trip point voltage to ensure that the differential input stage properly switches, or to ensure that the differential circuit does not switch too soon at a voltage less than the normal trip point voltage.)
It should be appreciated that the thermal time constants of recovery due to thermal imbalances in the integrated circuit chip are much longer than the electrical time constants of the signal/conditions which actually cause the thermal imbalances. The long thermal time constants therefore can be thought of as representing or causing secondary electrical signal paths having different electrical characteristics and longer recovery time constants than the primary electrical signal paths that exist when there is no thermal imbalance. Consequently, the transfer characteristic of an integrated circuit does not recover from a thermally imbalanced condition of the integrated circuit chip to its original configuration until amounts of time equal to the thermal time constants have elapsed after the modulating signal has returned to the low value.
The thermal imbalance effects mentioned above often are caused by “third-order” device topography features that are not easily modeled for circuit simulation purposes. The applicants are unaware of any available circuit simulation tools that accurately model the effects of thermal imbalances in typical integrated circuit layout arrangements.
It should be appreciated that problems caused by the thermal imbalances resulting from “self-heating” due to signal imbalances or offset voltages can be several orders of magnitude greater for SOI (silicon on insulator) integrated circuits than for junction-isolated integrated circuits because in SOI structures each circuit element is bounded by an oxide insulator which has a very large thermal resistance, and hence a very large corresponding thermal time constant.
A important type of thermal imbalance in integrated circuits is caused by differential thermal self-heating in the locations of the differentially coupled input transistors of amplifiers and comparators as a result of differential currents which flow through the input transistors as a result of differential input signals applied to differentially coupled input transistors and/or as a result of input offset voltages associated with the differentially coupled input transistors.
Various techniques have been used to partially overcome problems associated with differential mismatching between devices such as differentially coupled input transistors of an integrated circuit amplifier or comparator. One technique for dealing with an input offset voltage is to cascode the collectors or drains of the mismatched input transistor pair. This effectively reduces the magnitudes of the differential static and dynamic voltages across the mismatched input transistors and shifts a substantial amount of the differential power dissipation from locations of the input transistors to the cascode transistors. In some cases the offset voltage associated with the cascode transistors may contribute as much or more to the input-referred offset voltage of the integrated circuit as the mismatch between the base-emitter turn-on voltages of the input transistors.
Differential self-heating in the cascode transistors can affect other electrical parameters (such as transistor current gain) more than the offset voltage between them, and can cause offset errors to be “referred” back to the input of the amplifier circuit. (There are several known cascoding techniques, including (1) applying fixed bias voltage on the base or gate electrodes of cascode transistors, (2) providing “floating” cascode transistors in which the bias voltage applied to the base or gate electrodes of the cascode transistors is referenced to the emitter or source electrodes of the mismatched input transistors being cascoded to maintain low fixed voltages across them, (3) providing folded cascode circuitry, and (4) providing floating folded cascode circuitry.) A technique for reducing power in an integrated circuit has been to turn off bias circuitry during certain circuit operating conditions. For example, comparators in some synchronous systems have been temporarily un-biased after their output values have been latched into flip-flops, to reduce power consumption and the effect of associated thermal imbalances in the comparator input transistors.
FIG. 2B shows a continuous closed-loop amplifier circuit in which an output of an operational amplifier 1A is connected by a feedback resistor RF to the (−) input thereof. The (−) input also is connected by an input resistor Rin to ground, and the (+) input is connected to receive a square-wave input pulse, as illustrated. If the output Vout is slew-limited, it has the appearance indicated by the solid-line waveform A. The feedback of Vout to the (−) input results in the error signal indicated by the solid-line waveform B between the (−) and (+) inputs, as illustrated. This is the case for typical high-precision integrated circuit operational amplifier designs, and results in an extended imbalance between the (−) and (+) inputs and consequently causes an extended thermal imbalance condition. The slew-limited response of Vout causes the error signal between the (−) and (+) inputs to have the illustrated somewhat sawtooth-like waveform as a result of delay in the slew-limited Vout signal relative to Vin, wherein the amount of the thermal imbalance is generally indicated by the area under the error signal. This causes thermal imbalance in the amplifier input stage to exist for an extended amount of time.
It should be appreciated that those skilled in the art sometimes deal with self-heating problems in a transistor by increasing the transistor size to reduce the maximum temperatures, but in many cases increased transistor size unacceptably reduces circuit speed. Sometimes fixed-current load devices are used and successive differential amplification stages are added to overcome thermal imbalance problems, but at the cost of increased circuit complexity.
In the case where Vout is not slew-limited, then Vout as shown in FIG. 2B has the shape indicated by the dashed-line waveform C, which results in the error signal indicated by the dashed-line waveform D. The error signal may have much higher peaks but be much narrower in this case, and may result from substantially larger currents in the amplifier input stage. However, the integrated energy under the error curve will be about the same both in the slew-limited case and in the non-slew-limited case, relatively independently of the slew rate.
FIG. 2C shows a conventional sample/hold amplifier 70 which includes a transconductance stage 71, an amplifier stage 73, and a sampling switch circuit 72 connected between the output of transconductance stage 71 and the (−) input of amplifier stage 73. The (+) input of amplifier stage 73 is connected to ground, and its output Vout is fed back to the (−) input of transconductance stage 71 and to one terminal of a holding capacitor CHOLD the other terminal of which is connected to the (−) input of amplifier 73. An input signal Vin is coupled to the (+) input of transconductance stage 71 as illustrated, and sampling switch 72 is controlled by a HOLD signal applied to a control terminal 74 of sampling switch 72, as illustrated. The feedback of the Vout signal resulting from the broken feedback loop when sampling switch 72 is opened results in an error signal as illustrated between the (−) and (+) inputs of transconductance stage 71 which may cause severe thermal imbalance in the integrated circuit chip. This sample/hold amplifier is characterized by an error signal with large deviations and long dwell times, so the integration of power under the error signal is very large.
The graph of FIG. 2D includes simulated curves that illustrate the contributions of various portions of the circuit shown in prior art FIG. 2A to the recovery time of Vout. Curve A shows that a simulation of Vout is unaffected by thermal imbalance if simulation of self-heating effects are not somehow superimposed on the circuit simulation. Curve B illustrates the recovery of Vout if only the effect of thermal imbalance between the input transistors Q1 and Q1 is simulated (by adjusting appropriate parameters in the transistor circuit model used in the circuit simulation program) in accordance with temperature values used in the thermal simulation model. Similarly, curve C illustrates the recovery of Vout if only the effect of thermal imbalance between the cascode transistors Q5 and Q6 is included in the simulation, and curve D illustrates the recovery of Vout if the effect of thermal imbalances between input transistors Q1 and Q2, load transistors Q11 and Q12, and cascode transistors Q5 and Q6 are included in the simulation of Vout.
Prior techniques are known for switching the amplifier signal path back and forth between separate differential input stages of a single operational amplifier. For example, the assignee's line of SWOP AMP operational amplifiers (“switchable op amps”) uses this technique. However, the switching of the differential input stages therein is performed in response to a timed external signal, such as a clock signal or a control signal, and the purpose of the switching function is to implement multiple gains and other signal processing options, and is not for the purpose of affecting thermal performance.
However, the present inventors believe that the magnitude of the thermal imbalances caused by imbalanced signals are offsets are not generally recognized in integrated circuit industry, and that the improvements in circuit performance that might be achievable by overcoming these problems also are not generally recognized in the integrated circuit industry.
In some applications, sampling or under-sampling is performed wherein inaccuracies due to thermal imbalances create signal distortion effects in circuits such as ADCs, digital radios, and the like which are very sensitive to signal distortion and result in frequency spectrum “products” that are difficult to distinguish from the intended signal.
Many amplifiers and precision analog processing circuits and signal processing circuits have a power-down or shut-down mode in which part or all of the circuit goes into a “sleep mode”. When the circuit “wakes up”, it may need to immediately begin very precise operation despite localized common mode self-heating that may exist and associated delay required for the circuit to recover to an equilibrium state. Such recovery can be unpredictable because when the power is first turned on, the circuit the inputs may be at undetermined levels which may result in thermal imbalance that is substantially worse than during normal operation of the circuit.
There appears to be no previously known practical solution to reducing the above described inaccurate circuit performance due to thermal imbalance caused by self-heating in an integrated circuit.
Thus, there is an unmet need for a circuit and technique for reducing or preventing transient or temporary power imbalances in an integrated circuit which cause transient inaccuracies in an output signal produced by the integrated circuit.
There also is an unmet need for a circuit and technique for reducing or preventing a transient or temporary power imbalance in a particular region of an integrated circuit which cause a thermal tail of a signal produced in the integrated circuit.
There also is an unmet need for a circuit and technique for reducing or preventing inaccurate switching due to a time-variable input offset caused by a transient or temporary power imbalance in a particular region of a comparator.
There also is an unmet need for a circuit and technique for reducing or preventing inaccurate operation of an analog-to-digital converter due to a transient or temporary power imbalance in a particular region of one or more comparators in the analog-to-digital converter.
There also is an unmet need for a circuit and technique for reducing or preventing undesirable effects of a transient or temporary power imbalance in a particular region of an integrated circuit due to an excessively large input signal.
There also is an unmet need for a circuit and technique for avoiding inaccuracy in analog signal sampling circuits due to transient thermal imbalances in the integrated circuit.
There also is an unmet need for a circuit and technique for providing fast recovery from power down or shutdown states in an integrated circuit.